(1) Field
This invention relates generally to memory products and relates more specifically to reference line structures associated with a reading cell.
(2) Description of the Prior Art
In a read operation of memory chips, a sense amplifier compares a reference signal, which is middle point between stored 1 and 0 signals, with a stored signal. There are various ways to provide such reference signals. FIGS. 1 a+b prior art show two examples used in conventional memories. For memories, in which an adjacent bit line to the accessed bit line can be used to put the reference signal, a pair of reference word lines is generally exploited. A folded bit line memory array is the typical example, and FIG. 1a prior art shows its scheme. For simplicity, one reference word line shown here is connected to one reference cell, but it is assumed that a middle point of stored 1 and 0 signals appears on the bit line when this reference word line is selected. When an even word line is accessed and the cell shown by a red dot is turned on. The stored signal, thus, appears on the bit line. Simultaneously, a lower one of the reference word line pair is tuned on to bring the reference signal on the adjacent bit line. According to the column address, multiplexer Mux 2 selects these two bit lines to connect to a sense amplifier. The sense amplifier compares two signals to judge read data as either 1 or 0. When an odd word line is accessed, an upper reference of the reference word line pair is selected. Thus, one pair of bit lines, which are adjacent each other, is always selected as inputs to the same amplifier that is shared in this array block
The second example shown in FIG. 1 (B) is based on a reference bit line. It is assumed that the middle point of stored 1 and 0 signals appears on the reference bit line. The array block shares this reference bit line, which is always selected to provide the reference signal to the sense amplifier. Depending on the column address, Mux selects accessed bit line to connect as the input to the sense amplifier
For reliable sensing, these reference lines mimic the line selected to read the cell content. Thus, precise tracking capability of all parasitic parameters on the reference line to the read line is very important. However, the conventional scheme is not optimized for this purpose. For example, in FIG. 1 (A), when a far end of word line to the reference word line is selected, parasitic parameters and AC and DC behaviors of the reference line are quite different from the accessed one.
The other point of the conventional reference schemes is yield issue. Since a large array block shares the reference line, when any defect hit it, the chip becomes dead.
The purpose of this invention is to realize reference lines for reliable sensing operations and to provide a means for yield enhancement.
There are known patents or patent publications dealing with reference line structures of semiconductor memory arrays:
U.S. Patent Publication (US 2010/0195422 to Imai) proposes a semiconductor integrated circuit including: a current difference sense type of a sense amplifier including: an input line connected to memory cells as a target to be read, a reference line connected to reference cells, and a first pre-charge circuit configured to pre-charge the input line and the reference line; a second pre-charge circuit configured to perform pre-charging of the input line and pre-charging of the reference line; and a control circuit configured to control the second pre-charge circuit so that the second pre-charge circuit may perform both the pre-charging of the input line and the pre-charging of the reference line independently of each other, and start both the pre-charging of the input line and the pre-charging of the reference line earlier than pre-charging by the first pre-charge circuit.
U.S. Patent Publication (US 2009/0067274 to Beer) discloses a memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of the bit line and the reference line. Inputs of the evaluation circuit are directly connected to the bit line. Outputs of the evaluation circuit are coupled to the bit line via a switch.
U.S. Pat. No. 6,930,922 to Mori et al. discloses a reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.